IBM Unveils Nanostack Chip Technology Extending Semiconductor Miniaturization

IBM has unveiled a groundbreaking chip architecture that could extend the life of Moore's Law by another decade. The company's new "nanostack" technology vertically bonds two layers of nanosheet transistors, packing nearly 100 billion transistors onto a chip the size of a fingernail—roughly twice the density of IBM's previous 2nm chip announced in 2021. The architecture promises up to 50% higher performance or 70% better energy efficiency compared with that benchmark.

"It's not just an incremental step, it's a meaningful leap forward," said Jay Gambetta, Director of IBM Research, during a press conference announcing the breakthrough. The technology, which IBM describes as the world's first sub-1 nanometer semiconductor technology, marks a fundamental shift in how chips are built—moving from horizontal scaling to vertical stacking.

The achievement comes at a critical juncture for the semiconductor industry. For more than half a century, chipmakers have followed Moore's Law—the principle that the number of transistors on a chip doubles approximately every two years. But in the last decade, transistors have approached the point where quantum mechanics begins to interfere with their function. At just a few dozen nanometers in size, they simply cannot get smaller through traditional horizontal scaling. IBM's nanostack offers a way forward by building upward rather than shrinking sideways.

Dan Hutcheson, Vice Chair of TechInsights, described the breakthrough as "transformational," noting that it puts "another 10, 15 years on the roadmap." The technology is the culmination of years of research at IBM's semiconductor facility in Albany, New York, conducted in partnership with ASML, Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions.

The Breakthrough: Building Up, Not Shrinking Down

IBM's nanostack architecture represents a fundamental departure from traditional chip design. Instead of continuing to shrink transistors horizontally—an approach that has become increasingly difficult and expensive—the company has developed a method for stacking transistors vertically, like a "block of flats" rather than spreading out like suburban housing.

The approach is rooted in the recognition that the semiconductor industry has reached the physical limits of horizontal scaling. Transistors have gotten close to the point where quantum mechanics starts to interfere with their function, making further miniaturization impractical. IBM's solution is to build up, using a three-dimensional architecture that "vertically stacks and staggers transistors" with 3D sequential integration.

The result is a chip that can pack nearly 100 billion transistors onto a piece of silicon the size of a fingernail. This represents roughly twice the transistor density of IBM's 2nm chip unveiled in 2021, which itself was a major milestone. The achievement is particularly significant because it was accomplished without the need for increasingly expensive and complex lithography equipment.

Professor Alan Woodward, a computer scientist at Surrey University, compared the approach to building a "100-storey skyscraper" while competitors like Samsung and Intel are working on "30-50 storey buildings" with their own 3D chip efforts. "I think it's fair to say IBM's proposals are the most ambitious," he told the BBC.

By the Numbers: What Nanostack Delivers

IBM's nanostack technology delivers impressive performance and efficiency gains that could transform computing across multiple domains.

According to IBM's projections, chips built with the nanostack architecture can do as much as 50% more work in the same amount of time compared with the company's previous 2nm technology. Alternatively, designers can choose to prioritize energy efficiency, achieving up to 70% better performance per watt. These gains are not just incremental—they represent a meaningful leap forward in computing capability.

The company also reported a 40% improvement in SRAM scaling, a significant achievement in its own right. Static random-access memory, the fast on-chip memory that is crucial for AI workloads, has stubbornly resisted shrinking in recent generations. While earlier node transitions from 3nm to 2nm delivered only a few percent improvement in SRAM scaling, nanostack achieves a 40% reduction in cell height. As Gambetta noted, "This achievement of 40% will eventually industrialize itself in AI workflows, which require higher bandwidth and high efficiency."

Huiming Bu, IBM's Vice President of Semiconductor Technology Research, explained that the nanostack architecture is "not a one-time innovation—it is a new transistor platform that enables so many innovations going forward." The platform approach means that the technology can be applied to many different types of chips, including CPUs, GPUs, mobile chips, and AI accelerators.

How It Works: A Layer-Cake Architecture

The nanostack architecture builds directly on IBM's earlier work with nanosheet transistors, which formed the basis of its 2nm node introduced in 2021. In the new design, the basic unit consists of two transistors stacked and bonded together, with each transistor made up of three nanosheets.

The engineers create the chip layer by layer, like a cake. They start by fabricating transistors on one layer of silicon. Then they place a silicon layer on top of these devices, and they fabricate another layer of transistors directly on top of that. Finally, they create the electrical connections between the two layers of transistors.

A key innovation is the use of wafer bonding for "sequential integration." This approach unlocks engineering flexibility not available in monolithic stacking methods. Because the top and bottom transistors are fabricated separately before bonding, their gate stacks, channel materials, and process conditions can be optimized independently.

"The top FET and the bottom FET can be developed and optimized independently," Bu explained. "That unleashes so many innovations you can introduce into this architecture."

The staggered channel design—in which transistors in the second layer do not sit directly on top of the first layer's transistors—simplifies wiring and improves area efficiency. According to results published at the VLSI 2025 symposium, the 7A nanostack design achieves approximately 50% area scaling versus the 2nm node.

IBM also developed a modified NFET replacement metal gate stack that remains thermally stable when subsequent top-FET processing steps expose it to elevated temperatures. This thermal compatibility was validated alongside CMOS inverter demonstrations confirming functional switching performance.

The Evolution of Chip Design: From Planar to Stacked

IBM's nanostack architecture is the latest chapter in the evolution of chip design. The following timeline traces the key milestones that have led to this breakthrough:

Each generation has addressed a specific challenge in the pursuit of better performance and efficiency. High-k metal gate dielectrics addressed leakage in planar devices. FinFET reduced leakage and enabled scaling below 20nm. Nanosheet provided better electrostatic control and became the foundation for the 2nm and 3nm nodes. Now, nanostack addresses the physical limits of horizontal scaling by moving into the third dimension.

As Bu explained, "When I hear semiconductor people say something is coming to an end, it doesn't mean progress stops. What it actually means is the technology has come to a point where we need a new paradigm. Today, for the first time in our industry's history, we are enabling transistor scaling in the Z direction."

The AI Connection: Why This Matters Now

IBM's nanostack architecture is being positioned as a key enabler for AI infrastructure. Both Gambetta and Bu emphasized AI computing as a primary application context, citing the technology's potential to address the power and performance demands of large language models and other AI workloads.

"Think about AI computing—everyone demands more performance, but no one wants to pay the power bill," Bu said. "This new innovation will deliver 50% higher performance compared to what's the best available chip today, and at the same time it can reduce power by 70% if you choose to manage your power budget."

The 40% SRAM scaling gain is particularly significant for AI accelerator design. On-chip memory capacity and bandwidth are persistent bottlenecks in AI systems, and the ability to pack more SRAM into the same footprint could dramatically improve AI performance. Gambetta noted that the improvement will "industrialize itself in AI workflows, which require higher bandwidth and higher efficiency."

According to projections cited in Chinese media reports, IBM expects that AI accelerator compute power could reach approximately six times current levels with the 0.7nm technology. Large language model training times could potentially be reduced from about three months to just weeks.

The technology is expected to be widely adopted in data centers within a decade, where improved efficiency could help facilities better manage their energy consumption. This is particularly important given the growing energy demands of AI systems and the increasing scrutiny of data center environmental impact.

The Path to Production: Challenges Ahead

While IBM's nanostack technology represents a major breakthrough, significant challenges remain before it can be commercialized. IBM expects the earliest commercial adoption within the next five years, but several hurdles must be overcome.

IBM's use of wafer bonding for sequential integration partially addresses some of these challenges by allowing the top and bottom transistors to be optimized independently. However, the fundamental physics of heat generation in stacked devices remains a concern, particularly for multiple layers.

Cost is another significant barrier. The semiconductor industry is already grappling with the enormous capital costs of advanced manufacturing. The current 2nm technology requires foundries costing approximately $28 billion, and nanostack manufacturing would require even more sophisticated facilities. This creates challenges for widespread adoption, particularly for smaller companies and foundries.

Qing Cao, a professor of materials science and engineering at the University of Illinois at Urbana-Champaign, described IBM's work as "transformative" because it demonstrates how to stack transistors "on a full wafer using a state-of-the-art manufacturing line." However, he noted that academic researchers are also working on alternative approaches, such as junctionless transistors that can be created below 200°C, which could be easier to scale to multiple tiers.

The Roadmap: A Decade of Scaling Ahead

IBM is presenting nanostack as a scalable platform rather than a one-generation advance. The company's roadmap projects continued scaling from the 7A node through 5 angstrom and 3 angstrom, with a long-term horizon extending to 1 angstrom—a projected decade or more of future scaling enabled by the architecture's inherent stackability.

"Nanostack is not one innovation," Bu said. "It is a device platform that can enable the future of scaling for another decade beyond nanosheet."

While the current demonstration stacks two transistors, IBM's technical assessment indicates the approach is compatible with multi-layer stacking in future generations. The company also addressed wafer cost concerns, noting that unipolar patterning of each transistor layer independently eliminates a significant number of lithography steps, partially offsetting the cost of the bonding process.

IBM expects nanostack to follow the adoption trajectory of nanosheet, which moved from IBM's research announcement to industry-standard architecture at leading foundries within roughly five years. By that timeline, nanostack could be in production by approximately 2031.

"It will replace nanosheet as today's mainstream in leading foundries, whether it's CPUs or GPUs," Bu said. "Within a decade, this will become another mainstream that we have invented and helped industry to transform."

For now, IBM's immediate focus remains on helping Rapidus, the Japanese foundry, successfully establish 2nm manufacturing capability. The company declined to specify how nanostack technology will be licensed or transferred to manufacturing partners, indicating that the details of industrialization will be addressed once the 2nm transition is complete.

IBM's nanostack represents a landmark achievement in semiconductor technology. As Professor Cao noted, "I'm interested in what's their killer application." The answer may lie in AI data centers, where the combination of higher performance and better energy efficiency could transform the economics of AI computing.